Field of the Technology
The invention relates to the field of semiconductor packaging, and more specifically to a package for a micro-electromechanical device. The state-of-the-art packaging technology is suitable for hermetic packaging of MEMS devices of different shapes and form factors, in particular three dimensional MEMS devices, such as a folded MEMS timing inertial measurement unit (TIMU) and MEMS atomic navigator.
Description of the Prior Art
Packaging for Micro-electromechanical systems (MEMS) and Integrated circuits (IC) is one of the most important manufacturing steps before bringing the product into the market. It is also the most expensive process in micromachining. The package provides the interface between the components and the overall system as well as servers for establishing an appropriate operating environment. Some MEMS devices can require specialized packages or packaging processes. For example, inertial sensors need to be hermetically sealed in order to protect the moving parts from environmental effect such as humidity and dust. In addition, most MEMS gyroscopes, oscillators and resonant type accelerometers require vacuum encapsulation. Therefore, unlike electronic packaging, where a standard package can be used for a variety of applications, MEMS packages tend to be customized.
Various packaging technologies have been developed for Integrated Circuits and MEMS. These can be grouped under two major categories according to fabrication process: Chip-level packaging as seen in FIG. 1a and wafer-level packaging as seem in FIG. 1b. Chip-level packaging allows for an improved time to market due to the capability of using a standard type of package. However, wafer-level packaging is generally more cost effective.
Chip-level packaging category includes all commercially available metal packages, ceramic and plastic packages. Different companies offer a wide range of standard metal, ceramic, and plastic packages for different MEMS/IC applications. This includes surface mount packages/surface mount devices (SMD), pin grid array packages (PGA), dual-in-line packages (DIP), leadless chip carriers (LCC), flat packs (F/P), and chip scale packages (CSP). Generally, the device is a die attached to the bottom of the package cavity, wire bonded to the bond pads and hermetically sealed using a lid. Commercially available packages usually come with flat ceramic, metal or glass lids.
Wafer-level packaging category includes thin film packaging and packaging, based on hermetic wafer-to-wafer bonding techniques. Various approaches have been developed for wafer-level thin film packaging of MEMS devices. In the prior art, an article entitled “A Low-Temperature Thin-Film Electroplated Metal Vacuum Package”, by Brian H. Stark and Khalil Najafi, Journal of Microelectromechanical Systems, vol. 13, No 2, April 2004, proposes an idea of a packaging technology that employs an electroplated nickel film to vacuum seal a MEMS structure on wafer level. The package is fabricated in a low-temperature 3-mask process by electroplating a 40 μm thick nickel film over an 8 μm sacrificial photoresist that is removed prior to package sealing.
Another example of the prior art, an article entitled “Mechanical Design and Characterization for MEMS Thin-Film Packaging” by Fabio Santagata et al., Journal of Microelectromechanical Systems, vol. 21, No. 1, February 2012, describes a thin-film encapsulation approach, using a 6 μm thick low-pressure chemical vapor deposited (LPCVD) silicon nitride capping layer and a silicon oxide sacrificial layer.
A number of approaches for hermetic packaging based on wafer-to-wafer bonding techniques have been described in literature, U.S. Pat. No. 8,685,776 B2 discloses a method for manufacturing hermetically sealed MEMS device. Fabrication process starts with etching the device layer of the first SOI wafer and releasing the sensor mechanical features, using hydrogen fluoride (HF) etching. The silicon cover wafer is then fusion or Au-eutectic bonded to the SOI wafer. Next, the handle layers of the cover wafer and the bottom SOI wafer are etched, using a conventional wet etching process. Metallization is then applied to form an electrical connection with the encapsulated device.
A successful wafer-level packaging method for integrated MEMS with CMOS has been introduced by S. Nasiri et at in U.S. Pat. US20050166677. The Nasiri-fabrication process involves fabrication of a silicon-on-insulator (SOI) wafer, where cavities are formed in the handle layer. The MEMS device is defined in the device layer, using DRIE. Then, the SOI wafer with the device definition is bonded directly to the AI electrical contact pads on the bottom CMOS wafer.
Yu-T. Cheng et at in “Vacuum Packaging Technology Using Localized Aluminum/Silicon-to-Glass Bonding”, Journal of Microelectromechanical Systems, vol. 11, No. 5, October 2002, describe a glass vacuum packaging method utilizing aluminum/silicon-to-glass bonding process. The packaging process starts with forming, the polysilicon interconnect line and microheater, followed by deposition of an oxide/nitride/oxide sandwich layer for electrical insulation. Next, aluminum and polysilicon layers are deposited and pattered. A Pyrex glass capsule is then bonded on top of the device substrate.